The present invention relates to a semiconductor memory device and an address counter for generating an internal address signal for the device and, more particularly, to a synchronous semiconductor memory device operating in synchronism with an external clock input and having an operation mode in which a burst address signal is generated by itself in the memory chip on the basis of an externally supplied address signal to perform a read/write.
The present invention also relates to a burst address counter for generating a burst address signal, which is used for, e.g., an SRAM (Static RAM) having an operation mode in which a plurality of data buses are used to parallelly process data for a plurality of addresses.
In a conventional semiconductor memory, when only a normal synchronous operation mode is required, an operation mode of single data rate (SDR) scheme is supported, in which 1-bit data per input/output terminal is read/written from/in a memory cell in synchronism with only the rise of an external clock input.
As one of high-speed semiconductor memory operation schemes, a burst mode operation has been proposed. In this burst mode operation, a burst address is generated by itself in the chip on the basis of an externally supplied address signal in synchronism with a clock signal to perform a read/write.
To generate a burst address, consecutive addresses are generated in accordance with predetermined regularity (linear mode or interleave mode) on the basis of a 1- or 2-bit burst address signal.
In the burst mode period, if the burst address signal is assigned to two lower bits A1 and A0 of, e.g., an 18-bit address signal, the 16 upper address signal bits other than the address signal bits are kept fixed.
In the linear or interleave mode, a lower bit of a burst address signal alternately has a value 0, 1, 0, 1, . . . (or 1, 0, 1, 0, . . . ) without repeating the same value.
A burst address is often assigned to lower bits of a column address of a memory cell because it is required to quickly switch the memory cell to be selected.
A column system for selecting a column has a larger margin in terms of timing than that of a row system for selecting a word line of a cell. For this reason, the entire operation speed can be increased by assigning a burst address which takes a time to generate to the column system.
In the following description and drawing, column address bits Y1 and Y0 correspond to the burst address bits A1 and A0, respectively.
Such a burst mode operation can be applied not only to the SDR operation mode but also to an operation mode of double data rate (DDR) scheme in which data is read/written in synchronism with the up-edge (rise) and down-edge (fall) of an external clock input.
For a memory having the DDR operation mode, the internal operation speed does not particularly increase. When data is read or written in synchronism with both the rise and fall of an external clock input at only an I/O buffer, the internal operation speed of the memory appears to double (data read/write rate doubles) when viewed outside the memory. As such a memory, an SRAM has been proposed.
In an SRAM having the DDR operation mode, data corresponding to a plurality of addresses are parallelly processed using a plurality of data buses. The internal operation itself such as an actual data write in a memory cell is performed at the same speed (frequency) as that of an external clock input. However, the data transfer rate is doubled by parallelly processing data corresponding to two addresses at once.
That is, in the SRAM having the DDR operation mode, the data bus in the memory is doubled, and cells designated by two consecutive addresses of a burst address are simultaneously selected for a write or read.
Many SRAMs having the DDR operation mode can select either the above-described DDR operation mode or SDR operation mode.
A method of generating a burst address will be described with reference to FIGS. 1 to 4.
(1) In the linear mode of SDR scheme, by a binary count-up operation from an external address input as a start address, the start address is sequentially incremented to change the burst address.
More specifically, as shown in FIG. 1, when the start address is (0, 0), the burst address changes in the order of (0, 0).fwdarw.(0, 1).fwdarw.(1, 0).fwdarw.(1, 1). When the start address is (0, 1), the burst address changes in the order of (0, 1).fwdarw.(1, 0).fwdarw.(1, 1).fwdarw.(0, 0). When the start address is (1, 0), the burst address changes in the order of (1, 0).fwdarw.(1, 1).fwdarw.(0, 0).fwdarw.(0, 1). When the start address is (1, 1), the burst address changes in the order of (1, 1).fwdarw.(0, 0).fwdarw.(0, 1).fwdarw.(1, 0).
(2) In the interleave mode of SDR scheme, a signal obtained by performing the binary count-up operation from the external address input as a start address to increment the start address is exclusively ORed with the external address input, so the burst address changes from the start address as shown in FIG. 2.
(3) In the linear mode of DDR scheme, as shown in FIG. 3, an address in the above-described linear mode of SDR scheme and an adjacent address, i.e., two consecutive address signals are paired and sequentially incremented from the start address to progress the burst address.
(4) In the interleave mode of DDR scheme, as shown in FIG. 4, an address in the above-described interleave mode of SDR scheme and an adjacent address, i.e., two consecutive address signals are paired and sequentially incremented from the start address to progress the burst address.
To generate a burst address signal in the linear mode, an arrangement shown in FIG. 5 can be used.
Of signal bits of an external address input, the signal bits A0 and A1 corresponding to each other are input to first and second registers 61 and 62, respectively, in synchronism with an external clock signal CK. The outputs from the registers 61 and 62 are input to first and second binary counters 63 and 64, respectively, in correspondence with each other.
In this case, the first binary counter 63 counts signal bits in synchronism with the rise of the external clock signal CK. The second binary counter 64 counts signal bits in synchronism with the rise of a clock signal 2.times.CK having a speed twice that of the external clock signal CK. A 2-bit count-up operation is performed by the two binary counters 63 and 64.
A 4-bit signal consisting of a 2-bit complementary signal output from the first binary counter 63 and a 2-bit complementary signal output from the second binary counter 64 is input to a decoder 65 as a NAND circuit group to generate four column decode signal bits Ac1 to Ac4.
However, as described above, operating the second binary counter 64 at a speed twice that of the external clock signal CK poses a problem of operation speed as the speed of clock signal CK increases, and therefore is inappropriate for increasing the memory operation speed.
The binary counter 63 or 64 uses, as the most common structure, a toggle (T) flip-flop (F/F) as shown in FIG. 6. The number of NAND gates used therefor is as large as six. Generation of a burst address signal is delayed due to the gate delay, and consequently, the memory operation speed (e.g., access time) is limited.
When the burst address counter is to generate a burst address signal in the interleave mode, an exclusive OR circuit is added to the output side of the arrangement as shown in FIG. 6 to perform exclusive OR between the address signal and the external address input. For this purpose, more gates are used in addition to the T F/F shown in FIG. 6. Generation of a burst address signal is delayed due to the gate delay, and consequently, the memory operation speed (e.g., access time) is limited.
As described above, in the burst address counter using the conventionally available binary counters, the number of elements used to generate a burst address signal in the linear mode of SDR scheme is large. Generation of the burst address signal is delayed due to the gate delay, and the memory operation speed is limited.
The number of elements used to generate a burst address signal in the interleave mode of SDR scheme is larger, so the memory operation speed is further limited.
To generate a burst address signal to selectively cope with the linear or interleave mode of SDR scheme, a logic gate must be added, resulting in more complex circuit arrangement. The number of elements to be used further increases to limit the memory operation speed.
To generate a burst address signal in the linear or interleave mode to selectively cope with the DDR operation mode or SDR operation mode of the burst address counter 2, the above-described problem becomes very serious.